One of the contenders for future semiconductor electronic packaging schemes is the chip cavity multilayer board. The structure basically comprises multiple layers of printed wiring board material with conductors on one or more major surfaces of each layer. The layers are bonded together by an appropriate adhesive. Included in the structure is a cavity where the semiconductor chip is bonded and electrically connected to pads on the various layers. This chip cavity multilayer board can then be attached to a standard printed wiring board including other components.
One of the problems associated with fabricating this structure involves bonding together the various layers. If not properly controlled, the adhesive tends to flow from between the layers of printed wiring board material into the cavity as a result of the application of heat and pressure during bonding. This results in tight manufacturing tolerances, since too little flow of the adhesive can result in lack of circuit encapsulation and voids between the layers.
It is, therefore, a primary object of the invention to provide a method of manufacturing multiple layer structures with cavities therein so as to prevent the flow of adhesive from between the layers into the cavity and yet insure adequate circuit encapsulation.
Another problem associated with fabricating this type of structure involves the bending and deformation of wire bonding pads during the bonding process. Deformed and distorted wire bonding pads are not suitable for automated wire bonding assembly of the chip.
It is, therefore, a secondary objective of the invention to provide a method of manufacturing multiple layer structures with cavities therein so as to prevent the bending and distortion of wire bonding pads that can interfere with automated wire bonding.